Effect of wearout processes on the critical timing parameters and reliability of CMOS bistable circuits

TL;DRAbstract

The objective of the research presented in this thesis was to investigate the effects of wearout processes on the performance and reliability of CMOS bistable circuits. The main wearout process affecting reliability of submicron MOS devices was identified as hot-carrier stress (and the resulting degradation in circuit performance). The effect of hot-carrier degradation on the resolving time leading to metastability of the bistable circuits also have been investigated. Hot-carrier degradation was identified as a major reliability concern for CMOS bistable circuits designed using submicron technologies. The major hot-carrier effects are the impact ionisation of hot- carriers in the channel of a MOS device and the resulting substrate current and gate current generation. The substrate current has been used as the monitor for the hot-carrier stress and have developed a substrate current model based on existing models that have been extended to incorporate additional effects for submicron de

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