Design and analysis of future memories based on switchable resistive elements
TL;DRAbstract
Resistive bistable thin film elements have a great potential for implementing non-volatile memories with extreme densities. This work investigates using the switching characteristics of these resistive switchable elements to implement active and passive memory arrays. First, different active memory architectures has been investigated analytically and numerically based on the resistive elements which are characterised through there hysteretic resistive I/V curve. A new active memory cell concept which uses a capacitor connected serially to the resistive element has been proposed as an alternative the conventional memory cell. This concept simplifies the manufacturing of the memory and makes it possible to generate a higher voltage than the supply voltage across the resistive elements. Passive memory architectures based on crossbar-arrays are very compact because they don’t include a transistor in the memory cells. Different active periphery circuits for the read and write operations has
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Resistive bistable thin film elements have a great potential for implementing non-volatile memories with extreme densities. This work investigates using the switching characteristics of these resistive switchable elements to implement active and passive memory arrays. First, different active memory architectures has been investigated analytically and numerically based on the resistive elements which are characterised through there hysteretic resistive I/V curve. A new active memory cell concept which uses a capacitor connected serially to the resistive element has been proposed as an alternative the conventional memory cell. This concept simplifies the manufacturing of the memory and makes it possible to generate a higher voltage than the supply voltage across the resistive elements. Passive memory architectures based on crossbar-arrays are very compact because they don’t include a transistor in the memory cells. Different active periphery circuits for the read and write operations has
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