Book Chapter10.1007/978-1-4757-3281-8_9

VERIS: An Efficient Model Checker for Synchronous VHDL Designs

Yiping Fan,Jinsong Bei,Jinian Bian,Hongxi Xue,Xianlong Hong,Jun Gu-2001-01-01

0

Chat with Paper

AI Agents for this Paper

No abstract available for this paper.

Keywords

Model checkingComputer scienceVHDLReachabilityProperty (philosophy)Symbolic trajectory evaluationLocalityFormal verification

Chat

Click to start Chat