A Test Model for Hardware and Software Systems

TL;DRAbstract

The paper is concerned with the general aspects of testing complex hardware and software systems. First a mapping scheme as a test model is presented for an arbitrary given system. This scheme serves for describing the one-to-one correspondence between the input and output domains of the system, where the test inputs and fault classes are also involved. The presented test model incorporates both the verification and the validation schemes for hardware and software. The significance of the model is that it alleviates the clear differentiation between verification and validation tests, which is important and useful in the process of test design and evaluation. On the other hand, this model provides a clear overview on the various purpose test sets, which helps in organizing and applying these sets. The second part of the paper examines the case when the hardware and software are designed by using formal specification. Here the consequences and problems of formal methods, and their impact

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