Design error diagnosis in digital circuits: the case of simple errors

TL;DRAbstract

Automatic diagnosis of design errors is an important problem in digital circuits CAD. Although automated synthesis tools are being used to generate "correct-by-construction" designs, these designs are still modified manually to perform small specification changes, or to enhance some critical design aspects. Verification tools can discover the existence of errors, but they give no information about their location or how to correct them, they give only counter-examples that witness the error. What designers commonly do is simulate their design with these counter-examples, and visually inspect the ciruit and trace each path in it. This operation takes a very long time which may be equal or even greater than the design time itself. In this thesis we present automated algorithms for the location and the correction of simple design errors in logic circuits under the single error hypothesis. The errors treated here are component replacement errors in combinational and sequential circuits, and

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