Fiber Coupled Sub-nanometer Heterodyne Displacement Interferometry

TL;DRAbstract

The integrated circuit industry builds integrated circuits (IC’s) by placing many layers of semi conductive material on top of each other, the smallest details in such a layer are called features. Each layer has its own specific layout and will form together with the other layers three dimensional structures such as transistors, diodes or resistors. The final result is an integrated circuit which is called a chip of which a large number of them are fabricated all at once on a round silicon wafer. A position error between these two layers is called an overlay error, the final chip might not function correctly or not at all if this overlay error exceeds certain limits. It is important to minimize this error to obtain a high yield per wafer. As the features are getting smaller in size, the position of a ’new’ layer with respect to the layer below becomes more critical. High end position measurement equipment is required to minimize this overlay error. The lithography-machines involved wit

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