An Ultra-Low-Power ADPLL for WPAN Applications

TL;DRAbstract

RF PLLs for frequency synthesis and modulation consume a significant share of the total transceiver power, making sub-mW PLLs key to realize ulp WPAN radios. Compared to analog PLLs, all-digital phase-locked loops (ADPLLs) are preferred in nanoscale CMOS, as they offer benefits of smaller area, programmability, capability of extensive self-calibrations, and easy portability. However, analog PLLs dominate the ulp arena, since the time-to-digital converter (TDC) of an ADPLL has traditionally been power hungry. In this work [1], an ultra-low power 2.1 GHz – 2.7 GHz fractional-N ADPLL is presented for wireless personal area network (WPAN) applications. A DTC-assisted snapshot TDC and a DC-coupled DCO buffer with a tunable voltage transfer characteristic (VTC) are proposed to lower the power consumption. The ADPLL prototype fabricated in TSMC LP 40 nm CMOS process consumes only 860 µW at 1 V supply, and has a measured rms jitter of 1.71 ps (integrated from 1k to 100MHz), leading to a state-

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