A high-level synthesis based VLSI design methodology

TL;DRAbstract

Though high-level synthesis tools seem to fit nicely into the traditional top-down VLSI design methodology in which an abstract algorithmic model is transformed into a detailed register transfer level implementation, there is an important difference between filling in the details by hand and relying on a high-level synthesis tool to do so. Unlike the hand-designer, an engineer who uses a synthesis tool is not likely to be familiar with the specific register transfer level implementation that is produced. Thus, the use of high-level synthesis tools can effectively inhibit the engineer's ability to attack design problems or make informed trade-offs at either the specification or implementation level. To enhance the potential for engineer involvement in the synthesis based design process we have developed a methodology that includes a new abstraction for modeling high-level synthesis specifications as well as results (called attributed-behavior), and a new high-level synthesis tool, base

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