Simulation of the Direct Execution of a Higher Order Language.

TL;DRAbstract

This thesis lists the results of a follow-on study of Phase II of the Space Programming Language Machine (SPLM) Architecture Study (AD-A002 798). In this follow-on study, the Clock Level Simulator (CLS) was translated to JOVIAL/J73 and improvements were made to decrease execution times and memory requirements of the simulator. This work was accomplished using the DEC-10 system of the AF Avionics Lab. at Wright-Patterson AFB. CLS simulates the direct execution of SPLML (Space Programming Language Machine Language) on an SPLM. SPLML is a higher order language that was developed especially for avionic applications. CLS was developed as a design tool where the memory word size, memory address size, etc. are design parameters which represents a specific configuration of an SPLM. CLS, therefore, is a preliminary model for a family of machines (SPLM) with varying capabilities and complexities. An example program execution is given in detail.

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