Using Thermal Stress Simulation to Estimate Stacked Memory Module Reliability Under Thermal Cycle Test

TL;DRAbstract

Thermal stress simulation is carried out to investigate the thermal cycle reliability of a stacked memory module. A newly-developed stacked memory module was applied to high performance electronic equipment, such as computers, switching systems and space systems. This module consists offour chip size packages (CSPs). In the CSP stacking process, solder ball bumps are used to connect signal pads on the carriers. Considering plasticity and creep of solder bump material, the three-dimensional finite element model for a stacked memory used in this simulation was built to have non-linear characteristics. The fatigue life ofa solder bump under a thermal cycle test was predicted from a simulated inelastic strain value by using the Coffin-Manson equation. In results, it was found that filling resin around all the solder bumps makes fatigue life more than 20 times longer than in a conventional no-resin structure. The optimum values for reducing solder bump stress and strain of two resin propert

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