Prospects and Development of Vertical Normally-off JFETs in SiC

doi:https://doi.org/10.26636/jtit.2009.4.958

Open AccessArticle10.26636/jtit.2009.4.958

Prospects and Development of Vertical Normally-off JFETs in SiC

Mietek Bakowski-2009-12-30-Journal of Telecommunications and Information Technology

TL;DRAbstract

This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25°C to 250°C. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.

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This paper reviews the prospects of normally-off (N-off) JFET switch in SiC. The potential of selected vertical JFET concepts and all-JFET cascode solutions for N-off operation is analyzed using simulations. The performance of analyzed concepts is compared in terms of blocking voltage, specific on-state resistance, maximum output current density and switching performance in the temperature range from 25°C to 250°C. The main objective of the analysis is to ascertain consequences of different design and technology options for the total losses and high temperature performance of the devices.

Keywords

JFETCascodeMaterials scienceVoltageOptoelectronicsComputer scienceElectrical engineeringElectronic engineering

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