TL;DRAbstract
This paper presents a high-speed Reed-Solomon (255, 239) decoder architecture using modified Euclidean algorithm. Using pipelined and architecture optimized multiplier, the key equation solver block can be implemented in low complexity and power. The proposed global optimizing algorithm is also used in syndrome computation block to reduce the circuit complexity. The results show that the complexity of key equation solver block has been reduced by 30% and that of syndrome computation unit been reduced by more than 20%. This Reed-Solomon decoder has been designed and implemented with TSMC 0.25μm CMOS technology and the port rate can be up to 2.5Gb/s.
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This paper presents a high-speed Reed-Solomon (255, 239) decoder architecture using modified Euclidean algorithm. Using pipelined and architecture optimized multiplier, the key equation solver block can be implemented in low complexity and power. The proposed global optimizing algorithm is also used in syndrome computation block to reduce the circuit complexity. The results show that the complexity of key equation solver block has been reduced by 30% and that of syndrome computation unit been reduced by more than 20%. This Reed-Solomon decoder has been designed and implemented with TSMC 0.25μm CMOS technology and the port rate can be up to 2.5Gb/s.
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