Estimation and design algorithms for the behavioral synthesis of asics

TL;DRAbstract

High-level synthesis is the process of generating a register-transfer level (RTL) description from a behavioral specification. High-level synthesis is regarded as a means of overcoming the VLSI design complexities currently faced by designers. In this thesis we focus on estimation and design algorithms for high-level synthesis. For a given behavioral specification, a combinatorially large number of alternate RTL designs can be generated. One objective of this research is to develop tools which allow designers to efficiently search the design space to locate candidate designs. The techniques proposed in this thesis predict the design space region satisfying design constraints. This speeds up the synthesis process significantly. The complexity of the design process forces practical synthesis systems to use heuristics for generating satisfactory designs. In this thesis we develop tools to provide accurate bounds against which the quality of the results generated by the synthesis heurist

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