Implementation of Combinational Automatic Test Pattern Generator D_Algorithm

TL;DRAbstract

Testing of combinational circuit is crucial important to ensure high level of functionality. As density of digital circuit increases rapidly day by day these increases cost and time to test a particular combinational circuit for testing such circuit we need high quality test vector pattern with minimum number of input combination. In this work, we are designing Automatic test pattern generator (ATPG) D_Algorithm which will generate a minimum number of input pattern to detect fault like stuck-at-0 fault, stuck-at-1 fault, short circuit fault. D_Algorithm has been design by writing practical extraction and report language script to generate VHDL coding which is simulated on Xilinx 9.1.

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