NoC characterization framework for design space exploration

TL;DRAbstract

A NoC is considered as the interconnect architecture for the future MPSoC. It should provide the required quality of service in terms of predictable guaranteed as well as best effort services to meet the application constraints. The application traffic patterns applied on a NoC is hard to predict due to dynamics of the application. A characterization framework is required for design space exploration of NoC architectures. This framework should be able to evaluate NoC performance for a set of applications. In this thesis we propose a NoC characterization framework for design space exploration called NoCExplorer. NoCExplorer is a cycle accurate simulator, developed using SystemC and VHDL. It supports individual blocks in the NoC to be synthesized or replaced with register transfer level VHDL code for mixed language simulations. NoCExplorer provides a rich set of performance parameters to analyze a NoC and can generate heat maps for visual representation of link utilization and router con

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