A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
2007 · 825 citations
https://doi.org/10.1109/iedm.2007.4418914
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76
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h-index
56
i10-index
K. Mistry is an academic researcher from Intel (United States). The author has contributed to research in topics: Semiconductor materials and devices & Advancements in Semiconductor Devices and Circuit Design & Integrated Circuits and Semiconductor Failure Analysis. The author has an h-index of 30, co-authored 65 publications.
ORCID: 0000-0001-6472-599Xhttps://doi.org/10.1109/iedm.2007.4418914
https://doi.org/10.1109/vlsit.2012.6242496
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