A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging
2007 · 825 citations
https://doi.org/10.1109/iedm.2007.4418914
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G. Ding is an academic researcher from Sinolight (China). The author has contributed to research in topics: Advancements in Semiconductor Devices and Circuit Design & Semiconductor materials and devices & Ferroelectric and Negative Capacitance Devices. The author has an h-index of 5, co-authored 6 publications.
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