0.18 µm 3.1–10.6 GHz CMOS UWB LNA with 11.4±0.4 dB gain and 100.7±17.4 ps group-delay
TL;DRAbstract
A 3.1–10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only ±17.4 ps across the whole band) using standard 0.18 µm CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S11) of −9.7 to −19.9 dB, output return loss (S22) of −8.4 to −22.5 dB, flat forward gain (S21) 11.4±0.4 dB, reverse isolation (S12) of −40 to −48 dB, and noise figure of 4.12–5.16 dB over the 3.1–10.6 GHz band of interest. A good 1 dB compression point (P1 dB) of −7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681×657 µm excluding the test pads.
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A 3.1–10.6 GHz ultra-wideband low-noise amplifier (UWB LNA) with excellent phase linearity property (group-delay-variation is only ±17.4 ps across the whole band) using standard 0.18 µm CMOS technology is reported. To achieve high and flat gain and small group-delay-variation at the same time, the inductive peaking technique is adopted in the output stage for bandwidth enhancement. The UWB LNA dissipates 22.7 mW power and achieves input return loss (S11) of −9.7 to −19.9 dB, output return loss (S22) of −8.4 to −22.5 dB, flat forward gain (S21) 11.4±0.4 dB, reverse isolation (S12) of −40 to −48 dB, and noise figure of 4.12–5.16 dB over the 3.1–10.6 GHz band of interest. A good 1 dB compression point (P1 dB) of −7.86 dBm and an input third-order intermodulation point (IIP3) of 0.72 dBm are achieved at 6.4 GHz. The chip area is only 681×657 µm excluding the test pads.
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