A re-configurable 4<sup>th</sup> order switched capacitor ΣΔADC for adjusting power and performance

TL;DRAbstract

A re-configurable MASH ΣΔ ADC is implemented in 0.18μm CMOS process. The proposed technique configures the ADC architecture for optimal power for specific resolution and applications. For high performance applications, the first integrator stage of the cascaded modulator may be constructed from larger transistors and capacitors to reduce thermal and op amp noise. However, this larger first stage also consumes more power than later stages constructed from smaller transistors and capacitors. Thus the first stage tends to provide a higher resolution while consuming more power than later stages, which have lower performance and lower power consumption. The principal advantage of this architecture is that the ADC is adaptable for applications with different performance and power consumption requirements. Although the ADC was designed for audio applications, this re-configurability is also useful for multimode communication systems.

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